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Ordering number : EN4356A
Monolithic Digital IC
LB1870, 1870M
Three-Phase Brushless Motor Driver
Overview
The LB1870 and LB1870M are three-phase brushless motor driver ICs that are optimal for LBP and LBF polygon mirror motor drive.
Package Dimensions
unit: mm 3147A-DIP28HS
[LB1870]
Functions and Features
* Single-chip implementation of all circuits required for LBP polygon mirror motor drive (speed control and driver circuits) * Low motor drive noise level due to the current linear drive scheme implemented by these ICs. Also, small capacitors suffice for motor output oscillation suppression, with certain motors not requiring these capacitors at all. * Extremely high rotational precision provided by PLL speed control. * Built-in phase lock detector output * Four motor speed modes set by switching the clock divider provided under internal clock/crystal oscillator operation. This supports 240, 300, 400 and 480 dpi. * Use of an external clock allows arbitrary motor speeds. * Built-in FG and integrating amplifiers * Full set of built-in protection circuits, including current limiter, undervoltage protection, and thermal protection circuits.
SANYO: DIP28HS
unit: mm 3129-MFP36SLF
[LB1870M]
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum output current Allowable power dissipation (1) Allowable power dissipation (2) Operating temperature Storage temperature Symbol VCC max IO max Pd max1-1 Pd max1-2 Pd max2 Topr Tstg T < 0.1 s Independent IC (DIP28HS) Independent IC (MFP36SLF) With an arbitrarily large heat sink Conditions
SANYO: MFP36SLF
Ratings 30 1.0 3.0 0.95 20 -20 to +80 -55 to +150
Unit V A W W W C C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
98HA (OT)/91494TH (OT) B8-1284, 1285/N2092TS A8-9121, 9122 No. 4356-1/10
LB1870, 1870M Allowable Operating Conditions at Ta = 25C
Parameter Supply voltage range 6.3 V fixed voltage output current LD pin voltage FGS pin voltage LD pin output current FGS pin output current Symbol VCC IREG VLD VFGS ILD IFGS Conditions Ratings 20 to 28 0 to -15 0 to +28 0 to +28 0 to +10 0 to +5 Unit V mA V V mA mA
Electrical Characteristics at Ta = 25C, VCC = 24 V
Parameter Current drain Symbol ICC Vsat1-1 Vsat1-2 Vsat2-1 Vsat2-2 IO (LEAK) VREG VREG1 VREG2 VREG3 ISVREG IB (HA) VHIN VICM VIOH VSD VSD Sine wave input Differential input: 50 mVp-p 50 3.5 -20 VCC = 20 to 28 V IO = 0 to -10 mA Design target value Design target value 0 70 Stop mode IO = 0.6 A, Rf = 0 IO = 0.3 A, Rf = 0 IO = 0.6 A, Rf = 0 IO = 0.3 A, Rf = 0 VCC = 28 V 5.8 6.3 Conditions min typ 22 max 32 Unit mA
[Output saturation voltage]: VAGC = 3.5 V Source (1) Source (2) Sink (1) Sink (2) Output leakage current [6.3 V fixed voltage output] Output voltage Voltage variation Load variation Temperature coefficient Short circuit current [Hall input block] Input bias current Differential input range Common-mode input range Input offset voltage [Undervoltage protection] Operating voltage Hysteresis [Thermal protection] Thermal shutdown operating temperature Hysteresis [Current limiter operation] Limiter [FG amplifier] Input offset voltage Input bias current DC bias level Output high level voltage Output low level voltage [FG Schmitt block] Input hysteresis (high to low) Input hysteresis (low to high) Hysteresis Input operating level Output saturation voltage Output leakage current VSHL VSLH VFGL VFGSIL VFGS (sat) IFGS = 4 mA IFGS (LEAK) VCC = 28 V 100 400 0.2 0.4 10 0 150 200 mV mV mV mVp-p V A VIO (FG) IB (FG) VB (FG) VOH (FG) VOL (FG) No external load No external load Design target value -10 -1 -5% 1/2 VREG +10 +1 +5% mV A V V 1.2 V VRF 0.52 0.58 0.63 V TSD TSD Design target value (junction temperature) Design target value (junction temperature) 150 180 40 C C 8.4 0.2 8.8 0.4 9.2 0.6 V V 2 10 350 VCC - 3.5 +20 A mVp-p V mV 6.8 200 200 V mV mV mV/C mA 1.8 1.6 0.5 0.25 2.5 2.3 1.0 0.7 100 V V V V A
VREG - 1.3 VREG - 0.8 0.8
Continued on next page.
No. 4356-2/10
LB1870, 1870M
Continued from preceding page.
Parameter [Error amplifier] Input offset voltage Input bias current DC bias level Output high level voltage Output low level voltage [Phase comparator output] Output high level voltage Output low level voltage Output source current Output sink current [Lock detector output] Output saturation voltage Output leakage current [Drive block] Dead zone Output idling voltage Forward gain Reverse gain Accelerate command voltage Decelerate command voltage Forward limiter voltage Reverse limiter voltage [Reference signal block] Crystal oscillator frequency Low level pin voltage High level pin voltage [External clock input block] External input frequency Input high level voltage Input low level voltage Input open voltage Hysteresis Input high level current Input low level current [N1 pin] Input high level voltage Input low level voltage Input open voltage Input high level current Input low level current [N2 pin] Input high level voltage Input middle level voltage Input low level voltage Input open voltage Input high level current Input low level current [S/S pin] Input high level voltage Input low level voltage Input open voltage Hysteresis Input high level current Input low level current VIH (S/S) VIL (S/S) VIO (S/S) VIS (S/S) IIH (S/S) IIL (S/S) V (S/S) = VREG V (S/S) = 0 V -400 3.5 0 3.5 0.27 4.0 0.4 155 -300 VREG +1.5 4.7 0.53 200 V V V V A A VIH (N2) VIM (N2) VIL (N2) VIO (N2) IIH (N2) IIL (N2) V (N2) = VREG V (N2) = 0 V -400 4.0 2.0 0 3.5 4.0 155 -300 VREG 3.0 +1.0 4.7 200 V V V V A A VIH (N1) VIL (N1) VIO (N1) IIH (N1) IIL (N1) V (N1) = VREG V (N1) = 0 V -400 3.5 0 3.5 4.0 155 -300 VREG +1.5 4.7 200 V V V A A fCLK VIH (CLK) VIL (CLK) VIO (CLK) VIS (CLK) IIH (CLK) IIL (CLK) V (CLK) = VREG V (CLK) = 0 V -400 External clock mode 500 3.5 0 3.5 0.27 4.0 0.4 155 -300 7000 VREG +1.5 4.7 0.53 200 Hz V V V V A A fOSC VOSCL IOSCH Crystal oscillator mode IOSC = -0.5 mA VOSC = VOSCL + 0.3 V 1 4.4 0.5 8 MHz V mA VDZ VID GDF+ GDF- VSTA VSTO VL+ VL- Rf = 22 Rf = 22 0.4 -0.6 5.0 0.5 -0.5 5.6 0.8 0.58 0.58 1.5 50 100 300 6 0.6 -0.4 V V V V mV mV VLD (sat) ILD = 5 mA 0.1 0.4 10 V A VPDH VPDL IPD+ IPD- No external load No external load VPD = VREG/2 VPD = VREG/2 1.5 VREG - 0.4 0.4 -0.6 V V mA mA VIO (ER) IB (ER) VB (ER) VOH (ER) VOL (ER) No external load No external load Design target value -10 -1 -5% VREG - 1.0 1.0 1/2 VREG +10 +1 +5% mV A V V V Symbol Conditions min typ max Unit
ILD (LEAK) VCC = 28 V
No. 4356-3/10
LB1870, 1870M
Pin Assignments
(Top view)
(Top view)
No. 4356-4/10
LB1870, 1870M Pin Functions
Symbol IN1 to 3+, IN1 to 3- OUT1 to 3 GND1 GND2 Rf VCC VREG OSC E. CLK FC EI EO LD PD N1, N2 S/S FGS FG OUT FG IN- AGC Hall element input Outputs Sub-ground Ground Output current detection Power supply Power supply stabilization output Crystal oscillator External clock Control amplifier frequency correction Error amplifier input Error amplifier output Phase lock detector output Phase comparator output Divisor switching Start/stop FG pulse output FG amplifier output FG amplifier input AGC amplifier frequency characteristics correction Connect a capacitor between this pin and GND2. Start on low. Stop on high or open. Pulse output following the FG Schmitt comparator. This pin is an open-collector output. A minimum amplitude of 400 mVp-p is required. On when the PLL phase is locked. This pin is an open collector output. PLL phase comparator output Connect a capacitor between this pin and GND2. Internal circuit power supply stabilization. 8 MHz max 7 kHz max Connect a capacitor between this pin and GND2. Function Notes Taken as high when IN+ > IN-, and as low otherwise. Capacitors are inserted between these pins and ground. Output block ground. Connect to GND2. Ground for circuits other than the output block. Connect a small resistor between this pin and ground. Set the maximum output current so that I OUT = 0.58/Rf.
Equivalent Circuit Block Diagram
No. 4356-5/10
LB1870, 1870M Sample Application Circuit
Clock Divisor Switching
Pin N1 H L H L -- Pin N2 H H L L M Divisor 2560 (5 x 1 x 512) 5120 (5 x 2 x 512) 4096 (4 x 2 x 512) 3072 (3 x 2 x 512) EXT. CLK
Note: An open input is taken as a high level input.
PLL servo frequency = (crystal oscillator frequency)/(divisor)
Crystal Oscillator Usage
No. 4356-6/10
LB1870, 1870M External Component Values (reference values)
Crystal (MHz) 3 to 4 4 to 5 5 to 7 7 to 10 C1 (pF) 39 39 39 39 C2 (pF) 82 82 47 27 R (k) 0.82 1.0 1.5 2.0
Note: Use a crystal that has a ratio of at least 1:5 between the fundamental f0 impedance and the 3f0 impedance.
Three Phase Logic Truth Table
H1 H H H L L L H2 L L H H H L H3 H L L L H H OUT1 L L M H H M OUT2 H M L L M H OUT3 M H H M L L
Columns H1 to H3 H: H+ > H- L: H+ < H- Columns OUT1 to OUT3 H: Source L: Sink
LB1870 Functional Description and External Components 1. Speed control circuit This IC provides high-precision stable motor control with minimal jitter by adopting a PLL speed control scheme. This PLL circuit compares the rising edge of the CLK signal with the falling edge of the FG Schmitt output and outputs that phase error. When an internal clock is used, the FG servo frequency is determined by the formula shown below. Thus the motor speed is determined by the number of FG pulses and the crystal oscillator frequency. fFG(servo) = fOSC/N fOSC: Crystal oscillator frequency N: Clock divisor 2. Three-phase full-wave current linear drive This IC adopts a three-phase full-wave current linear drive to hold motor noise to an absolute minimum. When switching the output transistor phase, it creates a two-phase excitation state, suppresses kickback, and smooths the output waveform. This suppresses motor noise. Note that since oscillation may occur with some motors, the capacitors C12, C13, and C14 (about 0.1 F) are connected between the OUT pins and ground. 3. Current limiter circuit The current limiter circuit limits the current (i.e., the peak current) to a level determined by the formula I = 0.58/Rf. A scheme in which the output stage drive current is limited is adopted for the limiting operation. Therefore, the phase compensation capacitor C7 (about 0.1 F) is inserted between FC and ground. 4. Grounding GND1 (pin 11 in the LB1870, pin 5 in the LB1870M) .........................................Output block ground (sub-ground) GND2 (pin 28 in the LB1870, pins 1, 2, 17 to 20, 35, and 36 in the LB1870M)..Control circuit ground. GND1 and GND2 should be connected on the circuit board by the shortest distance that occurs in the pattern. Also, the Rf resistor R8 ground node and the GND1 and GND2 pattern line should be grounded to a single point on the connector.
No. 4356-7/10
LB1870, 1870M 5. External interface pins * LD pin Output type: open collector Breakdown voltage: 30 V absolute maximum Saturation voltage manufacturing variation reference value (ILD = 10 mA): 0.10 to 0.15 V * FGS pin Output type: open collector Breakdown voltage: 30 V absolute maximum Saturation voltage manufacturing variation reference value (IFGS = 4 mA): 0.15 to 0.30 V A hysteresis comparator converts the FG amplifier output to a pulse signal to create the FGS output, which is used for speed monitoring. The pull-up resistor is not required if this pin is not used. * S/S pin (start/stop pin) Input type: A pnp transistor whose base is pulled up to the internal 6.3 V power supply through a 23 k resistor, and is pulled down to ground through a 40 k resistor. Threshold level (low high): about 2.8 V Threshold level (high low): about 2.4 V The LB1870 goes to stop mode with this pin in the open state. * CLK input pin Input type: A pnp transistor whose base is pulled up to the internal 6.3 V power supply through a 23 k resistor, and is pulled down to ground through a 40 k resistor. Threshold level (low high): about 2.8 V Threshold level (high low): about 2.4 V * N1 pin Input type: A pnp transistor whose base is pulled up to the internal 6.3 V power supply through a 23 k resistor, and is pulled down to ground through a 40 k resistor. Threshold level (typical): about 2.6 V * N2 pin Input type: The base of a pnp transistor is pulled up to the internal 6.3 V power supply through a 23 k resistor, and is pulled down to ground through a 40 k resistor. Threshold level (low high): about 1.5 V Threshold level (high low): about 3.6 V 6. FG amplifier R1 and R2 determine the FG amplifier gain, with the DC gain G being R2/R1. C2 and C3 determine the FG amplifier frequency characteristics, with R1 and C2 forming a high-pass filter and R2 and C3 forming a low-pass filter. Since a Schmitt comparator follows the FG amplifier directly, R1, R2, C2, and C3 must be chosen so that the FG amplifier output is at least 400 mVp-p. (It is desirable for the FG amplifier output to be set up to be between 1 and 3 V during steady state rotation.) The FG amplifier is often the cause when capacity becomes a problem in noise evaluation. One solution to that problem is to insert a capacitor of between 1000 pF and 0.1 F between FG OUT pin and ground. 7. External capacitors * C1 C1 is the AGC (automatic gain control) pin smoothing capacitor. This pin is an automatic gain control pin for holding the hall amplifier output amplitude fixed. This pin outputs the three-phase hall signal envelope, and is smoothed with a capacitor (about 0.1 F) since it has ripple. When the hall input amplitude is small, the AGC pin potential will rise, and when the input amplitude is large, the AGC pin potential will fall. * C10 C10 is required for fixed voltage power supply stability. Since the output from the 6.3 V fixed voltage power supply is supplied to all circuits within the IC, noise on this signal must be avoided. This power supply must be adequately stabilized so that malfunctions due to noise do not occur. * C11 C11 is required for VCC stabilization. Since, just as with C10, noise must be avoided, this capacitor is provided to adequately stabilize the power supply. The length of the pattern lines used to connect capacitors C1, C10, and C11 between their respective pins and GND2 must be kept as short as possible. C10 and C11 require special care, since the pattern line length can easily influence their characteristics.
No. 4356-8/10
LB1870, 1870M 8. Oscillator pin A crystal oscillator and an RC circuit is connected to the LB1870's OSC pin. To avoid problems when selecting the oscillator and the capacitor and resistor values, confirm these values with the oscillator's manufacturer. The pnp transistor and resistor circuit shown in the figure can be used to apply an external signal (of a few MHz) to the OSC pin. fin = 1 to 8 MHz Input signal level: High level voltage: 4.0 V minimum Low level voltage: 1.5 V maximum It will be necessary to insert a capacitor of a certain size if there is overshoot or undershoot in the input waveform. Contact your Sanyo representative for more information on this point if necessary.
VDD = 6.3 V typ. (5.8 to 6.8 V) VDD = 5.0 V typ. (4.5 to 5.5 V) Ra = 4.7 k Ra = 2.0 k Rb = 1.3 k Rb = 1.0 k
Use the LB1870 VREG output for the VDD = 6.3 V case. 9. IC internal power dissipation calculation example (calculated at VCC = 24 V, standard ratings) * Power dissipation due to current drain P1 = VCC x ICC = 24 V x 22 mA = 0.53 W * Power dissipation when a -10 mA load current is drawn from the 6.3 V fixed voltage power supply. P2 = (VCC - VREG) x I load = 17.7 V x 10 mA = 0.18 W * Power dissipation due to the output drive current (When IO = 0.1 A, the inter-coil voltage V Rm = Rm x IO, and the reverse voltage = 15 V) P3 = (IO/100) x [(VCC - 0.7 V) + ((VCC - V Rm)/2) - 0.7 V] + VCC2/16 k = 1 mA x (23.3 V + 3.8 V) + 24 V2/16 k = 0.06 W * Power dissipation due to the output transistor (When IO = 0.1 A, the inter-coil voltage V Rm = Rm x IO, and the reverse voltage = 15 V) P4 = (VCC - V Rm) x IO = 9 V x 0.1 A = 0.9 W Therefore, the IC's total power dissipation is: In stop mode: P = P1 + P2 = 0.71 W In start mode (When IO = 0.1 A, the inter-coil voltage V Rm = Rm x IO, and the reverse voltage = 15 V) P = P1 + P2 + P3 + P4 = 1.67 W
No. 4356-9/10
LB1870, 1870M 10. Measuring the IC's temperature rise * Thermocouple measurement When using a thermocouple for temperature measurement, attach the thermocouple to a heat sink fin. This temperature measurement technique is straightforward. However, a large measurement error occurs when the heat generation is not in a steady state. * Measurement using IC internal diode characteristics We recommend using the parasitic diode that exists between LD and ground in this IC. Remove the external resistor when measuring. (Sanyo data indicates that ILD = -1 mA, about -1.9 mV/C, when the LD pin is high.) 11. Servo constants The servo constant calculation varies significantly with the motor used, and requires specialized know-how. Thus this should be handled by the motor manufacturer. Sanyo can provide the required IC characteristics data for servo constant calculation, and the motor manufacture should provide the frequency characteristics simulation data for the specified filter characteristics.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of July, 1998. Specifications and information herein are subject to change without notice. PS No. 4356-10/10

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